1. Field of the Invention
The present invention relates generally to antenna tuning circuits, and more particularly, to methods and systems for converting a balanced differential signal to an unbalanced signal and applying bias for active circuits.
2. Description of the Related Art
Transceiver power efficiency is greatly dependant on the efficiency of the transmitter power amplifier (PA). An efficient PA converts as much of the power supply direct current to RF output as possible. PA efficiency is especially important in portable transceiver systems that rely on a portable power source (e.g., battery) or other transmitters that have a limited power supply. Many portable transmitters are manufactured as highly integrated circuits (i.e., transmitter on a chip) so as to exploit the power efficiencies of integrated circuit design.
Some of the potential transmitter inefficiencies can be eliminated or significantly reduced in the design of the integrated power amplifier components. However, an integrated PA must still be connected to an antenna, impedance matching network, balancing circuits and other components that are external to the integrated transmitter on a chip. The parasitic capacitance in the output of the on-chip PA may not effectively be compensated for on the chip. This can be due to loss in signal power in resistive losses of on-chip passive components and ineffective use of silicon area due to large tuning components.
FIG. 1 shows a block diagram of a typical prior art transceiver 100. The transceiver 100 includes an integrated transmitter 104 that includes a differential power amplifier 110. The transceiver 100 also includes a front-end circuit 102. The front-end circuit 102 includes a balun 114. The differential PA 110 has a positive potential output 110p (positive port) and negative potential output 110n (negative port). The outputs 110p 110n of the PA 110 are coupled to the corresponding inputs 114p, 114n of the balun 114. The output 114A of the balun 114 is coupled to an antenna port 120.
The balun 114 is a balanced signal to unbalanced signal converter circuit that converts the balanced input signals 110n, 110p to an unbalanced or single pole output signal 114A, such as may be coupled to the single pole antenna port 120 to output a transmitter output signal.
FIG. 2 is a schematic of a typical three-line coupled balun 114. The balun 114 includes three lines 202, 204, 206 that are arranged to couple RF. Typically, each of the three lines 202, 204, 206 have a length of a quarter wavelength (λ/4). The first line 202 is connected to the positive port (i.e., positive differential output) 110p of the PA amplifier 110 at a first end and allowed to float, unconnected at a second end. The second line 204 is connected to the negative port (i.e. negative differential output) 110n of the PA amplifier 110 at a first end. A second end of the second line 204 is connected to a ground potential. The third line 206 is connected to the antenna port 120 at one end while the second end of the third line 206 is connected to a ground potential.
In a typical application such as in a 2.45 GHz transmitter output circuit, each of the lines 202, 204, 206 has an electrical length of a λ/4 or about 11 millimeters in a material with an effective dielectric constant of about 7.8. In a typical strip-line application the lines 202, 204, 206 are straight layouts that are arranged side by side in one conductive layer or are vertically aligned in adjacent metal layers. A straight line that is 11 mm in length is very large when compared to the physical size of a typical highly integrated transceiver 100.
DC power for the power amplifier devices 110 is typically supplied to the balun and to the PA through the output ports 110p, 110n. However, because the lines 202, 204 are not actually electrically connected as a DC path, then each of the PA output ports 110p, 110n require separate DC bias circuits.
Referring again to FIG. 1 above, each of the components in the front-end circuit 102 (e.g., the balun 114, the antenna 120 and the interconnecting conductors) has some level of parasitic capacitance that can load or otherwise degrade the efficiency of the PA 110. Similarly, each of the DC bias circuits can introduce imbalances in the PA output ports 110p, 110n. Requiring two DC bias circuits doubles the complexity of the DC bias circuitry, thereby doubling the resulting parasitic capacitance of the DC bias circuitry. Requiring two DC bias circuits also increases the likelihood of unintentionally introducing circuit imbalances to the PA output ports 110p, 110n that can be caused by even relatively slight differences in the two DC bias circuits.
In view of the foregoing, there is a need for a balun that allows a simplified DC bias path and is physically smaller than the prior art balun 114 while still maintaining the RF port arrangement described in FIGS. 1 and 2 above.